1. Field of the Invention
This disclosure relates to semiconductor devices. More particularly, this disclosure relates to a method for forming a wiring of a semiconductor device, for example, such as a tantalum nitride wiring, capable of simplifying processes for forming a wiring and preventing failures of semiconductor devices using a novel tantalum precursor, a method for forming a metal layer of a semiconductor device and an apparatus for performing the same.
2. Description of the Related Art
As computers have become widely used, memory devices using semiconductor devices have been remarkably developed. These semiconductor devices must operate at a high speed and simultaneously have a great amount of storage capacity. Technology has been developed to improve the integration degree, reliability, and response speed of a semiconductor device.
Forming a wiring in a semiconductor substrate is required to embody the semiconductor device on the substrate, because the wiring is used to transmit an electric signal. The wiring needs to have a low electric resistance and a high reliability. As the semiconductor device has been highly integrated the diameter of a contact hole has been reduced, and thus, the width and a thickness of the wiring have been also reduced. As a result, it has been more difficult to form a wiring.
According to the above description, a wiring including a metal layer used for a semiconductor devices must be strictly formed. Previously, a metal wiring including aluminum or tungsten is formed of with a multi-layered structure to raise the integration degree of a semiconductor device. However, since aluminum has a specific resistance of about 2.8×10−8 Ωm and tungsten has a specific resistance of about 5.5×10−8 Ωm, aluminum and tungsten are inappropriate for the metal wiring of the multi-layered structure. Copper is instead recently used for the multi-layered structure because copper has a relative low specific resistance and an improved electromigration characteristic.
Copper has a greater electromigration characteristic than silicon and silicon oxide. Accordingly, when copper reacts with silicon and silicon oxide, copper is readily oxidized. It has been shown to be preferable to use a metal barrier layer to prevent oxidation of the copper used in the wiring.
A titanium nitride layer has been widely used as the metal barrier layer. A titanium nitride layer of a thickness of above about 30 nm has been used to restrict the electro-migration of copper. However, a titanium nitride layer having a thickness of above about 30 nm has a high resistance because the resistance of the titanium nitride layer is proportional to the thickness of the titanium nitride layer. Additionally the titanium nitride layer has high reactivity. As a result, the titanium nitride layer is not well suited as a metal barrier layer.
A tantalum nitride layer is a better choice for the metal barrier layer of the copper. A thin tantalum nitride layer adequately restricts the electromigration of copper. Furthermore, the tantalum nitride layer has excellent step coverage, gap-filling characteristic, etc. Therefore, a tantalum nitride layer has been used as the metal barrier layer, as well as a metal plug, metal wiring, metal gate, a capacitor electrode, etc.
FIG. 1 is a cross sectional view illustrating a conventional method for forming a wiring of a semiconductor.
Referring to FIG. 1, an insulating layer 12 is formed on a substrate 10. A diffusion preventing layer including titanium nitride, a conductive layer including aluminum, an adhesive layer including titanium and a reflection preventing layer including titanium nitride are subsequently formed on the insulating layer 12. The diffusion preventing layer, the conductive layer, the adhesive layer and the reflection preventing layer are etched by a photolithography process to form patterns including a diffusion preventing layer pattern 13, a conductive layer pattern 15, an adhesive layer pattern 17 and a reflection preventing layer pattern 19. An insulating interlayer 21 is formed on the resultant structure. The insulating interlayer 21 is patterned using a photoresist pattern (not shown) to form a via hole 22 exposing an upper face of the reflection preventing layer pattern 19.
The photoresist pattern is removed by an ashing process. The organic material remaining on the upper face of the reflection preventing layer pattern 19 after the ashing process is removed by a wet cleaning process. Since the photoresist pattern includes a photo acid generator (PAG) that generates an acid through a photosensitive reaction, an acid is generated by the photolithography process. When the wet cleaning process is performed under the condition including the acid, a cleaning solution is mixed with the acid to have a weak acidity. When the substrate is misaligned in the photolithography process, a defect such as a scratch may be formed on the reflection preventing layer 19.
Generally, aluminum used as the conductive layer pattern 15 has a strong crystallization property, and thus aluminum may have an uneven surface. Namely, a groove is formed in an interface between grains of aluminum. When titanium and titanium nitride are deposited on the surface of aluminum, a titanium layer and a titanium nitride layer formed in the groove may be thinner than a titanium layer or titanium nitride layer formed on the surface of aluminum.
When the wet cleaning process is performed, thin weak nitride layer may be attacked by the acid solution and then removed because the titanium nitride has a chemical tolerance relative to the weak acid solution. The titanium layer and the aluminum layer beneath the groove in particular may be attacked by the acid solution, thereby deepening the groove. When photoresist is later coated and patterned, the photoresist may remain in the deep groove. As a result, a ring defect may be generated along the interface between grains of aluminum.
The ring defect induces a short between metal wirings, thereby deteriorating characteristic and reliability of a semiconductor device. Furthermore, since the interval between the metal wirings is reduced due to the high integration of a semiconductor device, the ring effect is a greater problem. To overcome this problem, an oxide layer pattern is formed on a reflection preventing layer including titanium nitride. After a metal wiring is formed using the oxide layer pattern as a hard mask, the oxide layer pattern is removed. However, this solution complicates the formation of the metal wiring, as will be explained further.
In the multi-layered structure, a via plug for connecting between upper and lower wirings is formed in an insulating interlayer. When a via hole filled with the via plug is formed through the insulating interlayer, a reflection preventing layer or a conductive layer pattern beneath the reflection preventing layer is exposed through the via hole.
However, when the conductive layer pattern is exposed through the via hole, the reliability of the lower wiring may be reduced. This is caused by the minute groove formed in the interface between the grains of aluminum used for the conductive layer pattern. The minute groove may be not filled with the via plug so that a void causing an electrical failure of the via plug may be formed. Accordingly, the structure having the reflection preventing layer that is only exposed through the via hole may be widely used.
For example, as shown in FIG. 1, when the via hole 22 is formed through the insulating interlayer 21 to expose the reflection preventing layer 19, a recessed portion may be formed on a surface of the reflection preventing layer 19 because the reflection preventing layer 19 including titanium nitride has a low etching selectivity relative to the insulating interlayer 21 including oxide. The conductive layer 15 including aluminum may be even exposed. The reflection preventing layer 19 may have a sufficient thickness to prevent the exposure of the conductive layer 15. However, when the reflection preventing layer 19 has a sufficient thickness, filling the space between the wirings with the insulating interlayer 21 may be difficult and may create the aforementioned void.
Therefore, a new technology for forming a wiring is required to improve the reliability of a semiconductor device. A tantalum nitride layer has been used as a reflection preventing layer or a barrier layer.
A method for forming a tantalum nitride layer is disclosed in U.S. Pat. No. 6,204,204 (issued to Paranjpe et al.), U.S. Pat. No. 6,153,519 (issued to Jain et al.), U.S. Pat. No. 5,668,054 (issued to Sun et al.), etc. In a method disclosed in the U.S. Pat. No. 5,668,054, a tantalum nitride layer is formed by a chemical vapor deposition (CVD) process using terbutylimido-tris-diethylamino-tantalum ((Net2)3Ta=NtBu) as a reactant. The CVD process is performed at a temperature of above about 600° C. When the CVD process is performed at a temperature of about 500° C., the tantalum nitride layer has a specific resistance of above about 10,000 Wcm. Since the process is performed at a high temperature, a thermal attack may be applied to a semiconductor device making the CVD process more difficult.
Recently, an atomic layer deposition (ALD) method has been proposed as an alternating technology for the CVD process. There are merits to the ALD method in that the tantalum nitride layer may be formed at a relative low temperature and may have improved step coverage. Methods for forming tantalum nitride layer by an ALD process are disclosed in U.S. Pat. No. 6,203,613 (issued to Gates et al.) and a document of Kang et al., entitled “Electrochemical and Solid-State Letters”. According to Kang et al., a tantalum nitride layer having a specific resistance of about 400 μΩm may be formed by an ALD process using terbutylimido-tris-diethylamino-tantalum. Accordingly, the tantalum nitride layer having a low specific resistance may be formed at a low temperature.
However, a hydrogen radical created by a plasma-enhanced process is required as a reducing agent in the document. A power source is applied to a chamber to form the hydrogen radical. Thus, the method requires the control of the power source applied directly to the substrate. Since the power source is directly applied to a substrate, the substrate may be damaged.
Accordingly, a new method for forming a tantalum nitride layer is required, which is performed at a low temperature, and has improved step coverage and simple processing requirements.
A method for fabricating Ta(NC(CH3)2C2H5)(N(CH3)2)3 and a metal organic chemical vapor deposition (MOCVD) method using a precursor solution including the same are disclosed in Japanese Patent Laid Open Publication No. 2002-193981. According to the method, 1 mole of TaCl5, 4 moles of LiNMe2 and 1 mole Of LiNHtAm are reacted with each other in an organic solution at a room temperature to form a compound, which is then filtered. The organic solution is removed from the filtered compound to form Ta(NC(CH3)2C2H5)(N(CH3)2)3, which is then dissolved in an organic solution. Dissolved Ta(NC(CH3)2C2H5)(N(CH3)2)3 is deposited on a substrate loaded in a CVD chamber to form a tantalum nitride layer.
Ta(NC(CH3)2C2H5)(N(CH3)2)3 may be readily fabricated according to the method, but the Japanese Patent Laid Open Publication describes that the tantalum nitride layer is formed using only Ta(NC(CH3)2C2H5)(N(CH3)2)3. It may not be desirable to use only Ta(NC(CH3)2C2H5)(N(CH3)2)3 to form the tantalum nitride layer. Particularly, when the MOCVD process is performed on the substrate using only Ta(NC(CH3)2C2H5)(N((CH3)2)3, the pressure in the chamber is not sufficiently high and the MOCVD process may be ineffective.